lscpu - AMD Radeon Pro VII
Architektura: x86_64
Operační režim(y) CPU: 32-bit, 64-bit
Velikost adresy: 39 bits physical, 48 bits virtual
Pořadí bajtů: Little Endian
Počet CPU: 6
Seznam zapnutých CPU: 0-5
ID výrobce: GenuineIntel
Název modelu: Intel(R) Core(TM) i5-9600K CPU @ 3.70GHz
Rodina CPU: 6
Model: 158
Vláken na jádro: 1
Jader na patici: 6
Patic: 1
Stepping: 13
CPU relativní MHz: 66%
CPU max. MHz: 4600,0000
CPU min. MHz: 800,0000
BogoMIPS: 7399,70
Příznaky: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault ssbd ibrs ibpb stibp ibrs_enhanced tpr_shadow flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp vnmi md_clear flush_l1d arch_capabilities
Virtualizace: VT-x
L1d keš: 192 KiB (6 instancí)
L1i keš: 192 KiB (6 instancí)
L2 keš: 1,5 MiB (6 instancí)
L3 keš: 9 MiB (1 instance)
Uzly NUMA: 1
CPU NUMA uzlu 0: 0-5
Zranitelnost Gather data sampling: Mitigation; Microcode
Zranitelnost Itlb multihit: KVM: Mitigation: VMX disabled
Zranitelnost L1tf: Not affected
Zranitelnost Mds: Not affected
Zranitelnost Meltdown: Not affected
Zranitelnost Mmio stale data: Mitigation; Clear CPU buffers; SMT disabled
Zranitelnost Reg file data sampling: Not affected
Zranitelnost Retbleed: Mitigation; Enhanced IBRS
Zranitelnost Spec rstack overflow: Not affected
Zranitelnost Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Zranitelnost Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Zranitelnost Spectre v2: Mitigation; Enhanced / Automatic IBRS; IBPB conditional; RSB filling; PBRSB-eIBRS SW sequence; BHI SW loop, KVM SW loop
Zranitelnost Srbds: Mitigation; Microcode
Zranitelnost Tsx async abort: Mitigation; TSX disabled